DDR controllers improve performance of embedded DRAM interfaces

According to Synopsys, DesignWare reduces the latency and silicon area by up to 50% compared to its previous generations of ddr memory controllers. Both controllers deliver memory system performance of up to 2133Mbps, the maximum data rate of the ddr3 standard, and offer a broadly utilised DFI 2.1-compliant interface to the ddr PHY. Synopsys adds that they enable the integration of multiple ddr interfaces into one design, servicing a range of products with less risk and improved time-to-market. "As ddr sdram standards continue to proliferate, it is vital to provide designers with a ddr IP solution that can support the breadth of sdram options," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "The new DesignWare Universal ddr protocol and memory controllers help designers address the critical latency and silicon area demands of advanced SoCs while simultaneously optimising the utilisation of the memory channel bandwidth."