Eco friendly performance

An extension of the company's V850 and V850E architectures, the new 32bit core is said to be highly scalable to compete with 16 and 32bit devices, and, according to NEC, provides increased functionality while lowering energy requirements. The mcu provides two 32bit V850 cpu cores, said to deliver levels of 2.563 Dhrystone MIPS per MHz, while enabling low power consumption of 1.5mW per MIPS. The V850E2M core is also available as redundant core architecture. The redundant cores monitor each other at each instruction by executing the same programme code and using the same data. Critical faults can therefore be detected at a very early stage by hardware. The cpu core has been designed to support a multicore architecture in which each cpu has access to the same memory context. This makes it possible for the V850E2M dual core to provide the levels required for environments with processing performance of 2.563 Dhrystone MIPS per MHz per core while maintaining low power consumption. The V850E2M core incorporates safety features such as lock step implementation where two cores mirror the operations of the other and check if both come to the same conclusion.