Renesas upgrades RX core for better performance, lower power consumption
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Responding to growing demand for better processing performance in single chip microcontrollers, Renesas Electronics has developed a new high performance 32bit cpu core and says samples of devices featuring the core will be available in Q1 of 2014.
Called RXv2, the core offers 4.0 Coremark MHz, or 2DMIPS/MHz, and can run at clock rates of up to 300MHz when manufactured on a 40nm process. With enhanced dsp and fpu capabilities, the core is said to benefit applications such factory automation, motor control, signal analysis and connectivity.
The RXv2 core is backward compatible with Renesas' RXv1 core, which features in the RX family of 32bit mcus. The RXv1 core offers features such as variable byte instructions, a Harvard architecture and a five stage pipeline. The RXv2 core is said to build on this to deliver improved computing performance, power efficiency and high code efficiency via a dual issue pipeline structure and advanced fetch unit. Because the RXv2 core contains all the instruction sets available with the RXv1 core, legacy RXv1 applications will be binary compatible with the new core.
Processing efficiency has been increased by adding a dsp instruction and reducing the number of processing cycles required by the single precision floating point. The RXv2 features two dedicated 72bit accumulators and a single cycle MAC instruction and can perform dsp/fpu operations and memory accesses simultaneously.
A reduction in power consumption of 40% is expected compared to 90nm devices based on the RXv1 core.
