OpenLane 2 is a completely re-envisioned infrastructure that the company says will help to open up new possibilities for development engineers and EDA tool developers to create custom flows, including highly specialised steps that were previously unattainable in the industry.
OpenLane is a Python-based infrastructure designed for implementing Application-Specific Integrated Circuits (ASICs). The platform has played a significant role in open-source silicon implementation since 2020. Integrating a range of development tools including Yosys, OpenROAD, Magic, and KLayout, it abstracts the complex processes of silicon design into tangible and manageable steps.
This approach has helped to make it the development backbone for numerous projects, including most projects on the Open MPW and chipIgnite shuttles.
OpenLane is described as being a community-centric platform that fosters collaboration and innovation in open-source hardware design and, through OpenLane 2, Efabless says that it is committed to pushing the boundaries of open-source hardware by providing a robust Python-based infrastructure upon which users can construct fully customisable flows incorporating both existing and novel steps using proprietary or open-source tools.
OpenLane 2 offers:
Stability and Flexibility: OpenLane 2 introduces a stable infrastructure that supports the creation of multiple, customisable flows. Whether it is integrating custom steps or leveraging advanced options for flow control, OpenLane 2 accommodates a wide range of user needs.
Enhanced User Experience: Users benefit from complete configuration validation, more graceful failure handling, and the flexibility to resume flows from specific stages – enhancing productivity and reducing time to implementation.
Customisability at Its Core: With OpenLane 2, users can write their own steps in Python, create complex flows with decision-making capabilities, and even experiment within Python Notebooks. This level of customisation was previously not possible.
The OpenLane 2 tool flow also includes a number of additional enhancements and benefits, including:
- Error-proof configuration and enhanced error handling
- Command-line flow control for nuanced workflow management
- Customisable and complex flows enabling optimal design strategies
- Access to a standardized and formalized form of design metrics
Mohamed Shalan, Head of the EDA/IC Design Team at Efabless, said, "OpenLane 2 is a testament to our commitment to innovation and collaboration in the open-source silicon space. By offering a silicon development infrastructure that supports highly customisable flows, we're not just meeting the current needs of the industry – we're also anticipating its future directions."
OpenLane 2 is now available.
