High-aspect ratio Ru lines were shown to outperform conventional Cu metallization in two different implementation scenarios, one in buried power rail applications and, in another, as interconnects for advanced memory and logic applications by using subtractive metal etch.
Due to an increasing resistance-capacitance delay and rising reliability concerns, the use of dual-damascene Cu as a process flow for back-end-of-line interconnect fabrication has become questionable beyond the 5nm technology node. To maintain the scaling paths, imec has been pioneering and pipelining the potential replacement of conventional Cu technology.
Interconnects based on Ru are seen as a promising candidate, because of their resistance to oxidation, high melting point, low bulk resistivity, and the ability to build barrier-less interconnect modules.
Commenting Zsolt Tokei, Distinghuished Member of the Technical Staff at imec, said: “For more than five years, imec has been systematically investigating this disruptive alternative, from the fundamentals to module level implementation. The results have recently come to the point of strong industrial interest.”
Imec used Ru-based interconnects in two different implementation scenarios. In a first application, Ru lines with aspect ratio (AR) up to
7 and critical dimension (CD) of 18nm were applied as a power rail, buried in the chip’s front-end-of-line oxide isolation. Traditionally, power rails are implemented as Cu lines in the metal-1 layer. The use of buried power rails has however recently emerged as a scaling booster, helping to minimise the standard cell height. Imec’s high-AR Ru lines, fabricated using a spacer defined integration scheme, exhibit low line resistivity of 8.8µΩcm, high stability, and withstand high temperature budget. With these characteristics, they can be used as a buried power rail in sub-5nm technology nodes.
In a second implemenation scenario, imec applied subtractive etch of Ru films to fabricate high-aspect ratio back-end-of-line interconnects for sub-5nm technology nodes. Imec demonstrated 12nm working Ru lines with aspect ratio up to 3.8, and line resistance below 500Ω/µm, and demarcated the technology targets for the 3nm node.
According to Tokei: “Our work proves that subtractive metal etch – which was used in the past for integrating Al interconnects – can be a valid alternative to the damascene implementation of Ru. The integration scheme has a strong downscaling potential, and can be considered for advanced memory and logic applications.”
Furthermore, using Si data and modelling, calibrated line and via resistance models have been developed for Ru, allowing to predict the resistance behaviour of Ru in future scenarios. Besides Ru, other pure metals, as well as graphene, binary and ternary compounds were found to potentially provide long-term material pipeline for interconnects.
