This latter service includes IP subsystem integration, PHY hardcore implementation, and signal integrity/power integrity (SI/PI) analysis on the system with package and PCB design.
Faraday has already successfully integrated the SerDes total solution into mass–produced ASICs for Fibre-To-The-Home (FTTH), home gateways, Ethernet switches, SSD, industrial automation, and 5G baseband, and other applications.
Combining silicon proved SerDes IP with Faraday's IPA service has helped to speed up the move by customers into mass production. The IP subsystem integration reduces the time needed to perform IP verification of interface protocol function in the system and the PHY hardcore implementation ensures the interface performance based on the customer’s dedicated configuration.
In addition, the IPA service provides the PCB layout guideline and supports the SI/PI analysis to increase data transfer throughput without system error. Using in-house IC Automatic Test Equipment (ATE) and compliance measuring instruments, the IPA service can accelerate the testing flow at different temperatures in the lab for bug-solving before mass production.
“Faraday's newly launched SerDes total solution is designed to accelerate customer's integration. This SerDes IP integrated with Faraday's PCIe Gen-4 PCS and controller IP has successfully passed the compliance tests held by PCI-SIG. We believe the total solution is an efficient and effective choice for applications that require SerDes,” said Flash Lin, COO of Faraday Technology.
Faraday’s SerDes IP at UMC 28nm is compliant with:
- PCIe Gen2/3/4 protocols
- Ethernet: 10G-KR, 40G-KR4/CR4, and 1000Base/SGMII
- xPON: 10GEPON, EPON, XGPON, XGSPON, GPON
