Floorplanner boosts SoC design efficiency
EDA start up Teklatech has launched FloorDirector at DATE in Munich. The floorplanning software is said to offer SoC power shaping, clock cycle stretching and robustness to on chip variation.
The tool combines power signature analysis and automated power peak reduction, providing more efficient SoC designs for a range of applications.
Until now, says Teklatech, semiconductor companies have had to solve power related issues at the physical level, incurring significant design risk and overhead. FloorDirector reduces dynamic IR drop and supply noise by intelligent power shaping, flattening power peaks, thus improving signal and power integrity. Dr Tobias Bjerregaard, Teklatech’s ceo, pictured, said: “Teklatech is sharply focused on meeting the difficult challenges of the semiconductor industry moving into the nanometer era. We believe we can drive the power/cost curve of designs at 90nm and below, enabling companies to eliminate costly silicon respins and achieve faster time to market.”
