The VP1902 is an emulation-class, chiplet-based device designed to streamline the verification of increasingly complex semiconductor designs. Offering 2X2 the capacity over the prior generation, designers will be able to innovate and validate application-specific integrated circuits (ASICs) and SoC designs to help bring next generation technologies to market faster.
AI workloads are driving increased complexity in chipmaking, requiring next-generation solutions to develop the very latest chips. FPGA-based emulation and prototyping can provide a high level of performance, allowing faster silicon verification and enabling developers to shift left in the design cycle and begin software development well before silicon tape-out.
“Delivering foundational compute technology to enable our customers is a top priority. In emulation and prototyping, that means delivering the highest capacity and performance possible,” said Kirk Saban, corporate vice president, Product, Software, & Solutions Marketing, Adaptive and Embedded Computing Group, AMD. “Chip designers can confidently emulate and prototype next-generation products using our VP1902 adaptive SoC, accelerating tomorrow’s innovations in AI, autonomous vehicles, Industry 5.0 and other emerging technologies.”
As complexity grows in ASIC and SoC designs, especially with the rapid advancement of AI and ML-based chips, extensive verification of both silicon and software before tape-out has become an essential requirement.
The VP1902 delivers both capacity and connectivity, delivering 18.5M logic cells for 2X2 higher programmable logic density and 2X4 aggregate I/O bandwidth compared to the previous generation Virtex UltraScale+ VU19P FPGA.
For pre-silicon verification and concurrent software development debugging is essential. Finding and addressing bugs before tape-out keeps programmes on schedule and budget. The VP1902 adaptive SoC leverages the Versal architecture, including the programmable network-on-chip, to provide up to 8X5 faster debugging compared to the prior generation VU19P FPGA.
The AMD Vivado ML design suite includes new features that support more efficient development on the VP1902 adaptive SoC such as automated design closure assistance, interactive design tuning, remote multi-user real-time debugging, and enhanced back-end compilation, which enables end users to iterate IC designs faster.
The AMD Versal Premium VP1902 adaptive SoC will begin sampling in Q3 to early access customers with production expected in the first half of 2024.
