Doug Amos, director of NMI’s FPGA Network, said: “Perhaps the most simple reason for the debug challenge is that design complexity is outstripping the capability of the verification tools used in FPGA projects. This year’s survey showed verification was a significant task and accounted for 24% of the time taken. However, the survey also showed that the most modern ASIC like verification techniques were not used widely.”
According to Amos, there may be light at the end of the tunnel. “At least one ASIC like technique has started to emerge: assertion based verification.” The most popular approaches were in system test, directed test and functional coverage.
A measure of the verification challenge was found by asking those responding to the survey about the non trivial bugs that made it into production. Some were obviously concerned about this issue, but perhaps a more worrying issue was that 11% of respondents admitted to ‘more than one’ non trivial bug entering production. And 51 respondents saw field upgradability as ‘essential’ to their design.
The most challenging prototyping specific tasks were found to be hardware visibility and debug, implementing externally developed IP and designing and building hardware using the latest FPGAs.
Asked how long their latest FPGA design project took, most answers suggested between 6 and 12 engineer-months; in last year’s survey, most projects were taking from 1 to 6 engineer-months.
Aerospace and defence remained the most popular application area for FPGAs, followed by industrial, video and image processing and ASIC prototyping. The survey found that 24% of FPGA design projects were targeted at devices with 100k to 500k LUT-FF pairs, but a significant number of designs (22%) were completed for devices offering 10k to 50k LUT-FF pairs. Two projects were using devices with more than 5million LUT-FF pairs. The dominant devices came from Altera’s Cyclone and Xilinx’ Spartan ranges.
Amos admitted to being ‘surprised’ at the popularity of ASIC prototyping, given the assumed low number of ASIC starts amongst UK companies. “This is probably explained by the use of FPGAs for prototyping IP and other sub blocks, which are designed here for use in ASIC and SoC projects elsewhere.”
The NMI FPGA Usage Survey 2015, supported by New Electronics, Aldec, Altera, FirstEDA, Mentor Graphics, Synopsys and Xilinx, drew responses from 154 users.
