Multi fpga partitioning software offers ‘unlimited design capacity’

Wasga Compiler is said to increase clock frequency by up to ten times and to handle multibillion gate asic designs, as well as map them to any Altera or Xilinx board. The company claims it is the first timing driven, multi fpga partitioning software for asic and SoC prototyping. The software automatically partitions large designs onto multiple fpgas while addressing chip resources, connectivity and clock frequency constraints. Maximising prototyping system performance, the developer says it helps to solve the hardware/software validation bottlenecks of next generation SoCs. "Multi fpga platforms are heavily used for asic and SoC rapid prototyping and existing tools notoriously fail the complex partitioning challenge. Verification engineers still rely on a cumbersome manual partitioning methodology," commented Flexras' ceo Hayder Mrabet. "Wasga Compiler complements fpga based SoC prototyping with high performance automatic partitioning. Engineers benefit from high clock frequencies, fast execution time and unlimited design capacity."