The GOWIN ISP IP core portfolio takes the pixel data from an image sensor and adjusts it through CFA (Color Filter Array/Debayer), CCM (Color Correction Array), Gamma correction, and AE (Auto Exposure) and AWB (Auto White Balance) to provide a much clearer image balanced in both colour and brightness.
The ISP IP core portfolio has been designed to offer camera and device manufacturers the ability to produce affordable camera products with a balanced high-quality picture. Imaging projects often use FPGAs to process imaging data at the streaming data rate as an alternative to fixed-function ISP cores in SoCs (System on Chip). As a result, GOWIN’s ISP IP core portfolio can be combined with video interface, scalar, and memory controller IP’s to create a complete programmable SoC solution tailored specifically to the needs of the application and product.
GOWIN provides the ISP IP cores individually in the GOWIN IP core generator. It also provides pre-generated IP cores integrated as part of a larger reference design to complete the image processing pipeline. The reference design also includes an ARM Cortex-M processor to control the image processing pipeline in real-time.
"GOWIN ISP can be configured and programmed through the embedded soft processor. It allows users to easily customise functions and tune ISP performance for their specific application scenarios to achieve better visual quality or higher recognition accuracy. I believe it can greatly shorten development and tuning time,” said Thomas Cheng, Director of Solution Development for GOWIN Semiconductor.
The ISP supports 8bit/10bit image data and provides an adjustable register map for different image sensors and resolutions. Calibration coefficients can be loaded by the MCU or initialized by the bitstream. IP modules in the pipeline can be intercepted allowing users to add their custom imaging blocks as needed.
