This integration, one of the first complete RISC-V microcontrollers in an FPGA, provides designers with the A25 processor power and the peripherals most processors require without consuming any FPGA resources. Consequently, the hardware team will be able to populate the FPGA with their value-added design while the software team can concurrently create application code based on the rich RISC-V ecosystem.
“Andes is committed to delivering cutting-edge RISC-V technologies allowing developers to create innovative and efficient solutions. The integration of the A25 RISC-V CPU and AE350 peripheral subsystem as a hard core in GOWIN Semiconductor’s GW5AST-138 FPGA marks a significant milestone in achieving this vision,” said Andes North America VP of Sales, Vivien Lin. “It provides our joint customers with a versatile hardware development platform to create, debug, and verify their ultimate SoC design before committing their netlist for silicon fabrication. For customers not requiring an SoC, it will enable a complete RISC-V computer ready to drive their end applications.”
"In the Arora V family, we incorporate the peripherals that a RISC-V CPU typically requires in hard instantiations," said GOWIN’s Sr. Director of Solution Development, Jim Gao. “We included a fully controllable high-speed SerDes for communication, video aggregation, and AI computing acceleration applications that demand very high data rates. Other instantiated functions include Block RAM modules supporting ECC error correction, high-performance multiple voltage GPIO, and high accuracy clock architecture. These hard functions save the FPGA programmable fabric of up 138K LUT’s for the designers’ unique logic implementation."
The AndesCore A25 hard core, running at 400MHz, supports the RISC-V P-extension DSP/SIMD ISA (draft), single- and double-precision floating point and bit-manipulation instructions, and MMU for Linux based applications.
The AE350 AXI/AHB-based platform comes with level-one memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components pre-integrated together as a system design. DDR3 controller and SPI-Flash controller in the FPGA fabric back up the A25's 32KByte I-Cache and D-Cache after cache misses.
Off chip DDR3 provides data memory, SPI-Flash contains the A25's instruction memory (codes copied from SPI-Flash into DDR3 and Cache upon boot-up).
Besides hard instantiated functions, the GOWIN GW5AST-138 FPGA fabric affords 138K LUTs for custom design implementation. GOWIN EDA provides an easy-to-use FPGA hardware development environment for the Arora V and supports multiple RTL-based programming languages, synthesis, placement and routing, bitstream generation and download, power analysis and in-device logic analyser.
