IEEE publishes new test and debug standard

Created to expand and improve JTAG (IEEE 1149.1) functionality, which has been in use for more than two decades, it is designed to maximise space and cost savings while maintaining previously made industry investments, as well as improving debug capabilities and power constraints for SoC architectures. It is not a replacement for the JTAG standard and maintains backward compatibility so a board that integrates chips that support either standard is amenable to test or debug procedures. Developed in an IEEE working group and led by Texas Instruments, the new standard enables manufacturers to accomplish more while using fewer resources. New features have been incorporated to address the need for complex digital circuitry, form factor size constraints and multiple cpus facilitated by smaller next generation consumer electronics. Stephen Lau, TI's emulation technology product manager, said: "IEEE 1149.7 offers a flexible, dynamic solution for designers and engineers contending with shifting design paradigms without eroding the firm foundation established by earlier standards such as IEEE 1149.1. The combination of an extraordinary level of customisability with already proven technologies, maximises IEEE 1149.7's effectiveness, ensuring its role as an essential, cost effective test and debug tool." Highlights of the new IEEE 1149.7 standard: • The ability to control debug logic power consumption in an industry standard way. Whereas IEEE 1149.1 (JTAG) had a single "always on" state, IEEE 1149.7 offers four selectable power modes to enable ultra-low power devices. • The ability to quickly access a specific device in a system with multiple devices. By implementing a system level bypass, the scan chain is drastically shorter, which directly improves the debugging experience. • The introduction of a star topology to complement the standard serial topology. Designers working with stacked-die devices, multi-chip modules and plug-in cards will favor the star topology because it simplifies the physical inter-device connections. • Two-pin operation instead of the four-pin operation required in IEEE 1149.1. Since most of today's systems integrate multiple ICs and often have severe size constraints, reducing the number of pins and traces will help designers meet their form factor goals and allowing for additional functional pins and/or low package cost. • Compatibility with existing IEEE 1149.1 (JTAG) compliant IP, allowing preservation of investment.