For Ge n-type FinFETs, pre-gate stack process optimisation tends to dramatically improve reliability and performance, with 100 percent improvement in positive bias temperature instability (PBTI) and improvement in GmSAT vs. SSSAT benchmark. For the Ge-based p-type GAA device, excellent short-channel control and performance have now been achieved with an improved extension-less junction scheme. The results confirm the potential of Ge-based CMOS transistors as high-performance solutions for the 3nm and beyond technology nodes.
Due to the higher intrinsic mobility of Ge compared to Si, Ge-based FinFET devices have now emerged as non-disruptive performance boosters for future technology nodes. While Ge p-type FinFET devices have been extensively studied, the development of well-performing, reliable Ge n-type FinFET devices has been lagging. Imec has now proposed an optimised process flow for the gate stack, solving one of the major challenges for Ge n-type FinFET development.
Key to the successful gate stack formation are an improved pre-cleaning and an optimised dummy gate oxide deposition and removal process, as part of a replacement metal-gate (RMG) process flow. The process flow resulted in 100 percent improved positive bias temperature instability (PBTI) and a 100% improvement in GmSAT vs. SSSAT benchmark – a measure for the interface quality and electron mobility.
“With our process flow, the oxide-free Ge channel surface can be prepared prior to the gate and efficiently protected from oxidation”, explained Naoto Horiguchi, logic program manager at imec.”
Improved performance and reliability of the Ge nFinFET device. (Left:) Best ID-VG curves obtained from 35nm-wide Ge nFinFET with dummy gate oxide and extended in-situ clean. (Right:) Extrinsic GmSAT vs. SSSAT benchmark of n-channel Ge fin and nanowire FETs at VDD=0.5V.
imec has also unveiled an improved junction scheme to solve one of the major challenges for p-type strained Ge-based GAA devices, i.e. achieving good short channel control while preserving transistor performance. A dramatic improvement in short channel control – allowing gate length scaling down to 25nm – was achieved by using an extension-less scheme, i.e., without dopant implantation in the ‘extension’ region next to the gate.
To maintain the transistor’s performance, the extension-less scheme was combined with spacer thickness reduction, and with the implementation of highly boron-doped Ge or GeSn as source/drain material. The optimised process flow resulted in a 55 percent improvement in GmSAT Vs. SSSAT benchmark on Ge GAA devices as compared to previous work. Short channel (LG~25nm) device also shown excellent Gm (Gm,lin=512µS/µm, Gm,sat=2220µS/µm).
Commenting Horiguchi said: “Ge GAA devices have the potential to further extend gate length scaling beyond what is possible with Ge-based FinFETs. They can be fabricated by using a process flow that is not so disruptive compared to FinFET processing. And much of the learnings we obtain from FinFET development can be transferred to GAA devices. By using our extension-less scheme, we have now demonstrated the feasibility of these Ge-based GAA devices for gate length scaling down to 25nm, while preserving excellent performance.”
(Left:) Median SSSAT versus physical gate length for strained p-type Ge GAA devices with double nanowires. Significantly improved electrostatic control below LG=40nm. (Right:) Best ID-VG characteristic of 9 nm wires diameter Ge GAA with 25 nm gate length by using extension-less scheme and scaled 8 nm spacer. The reported data are normalized to the total effective channel perimeter.
