imec debuts first strained germanium FinFETs

Integrated on 300mm Si wafers, the FinFETs been proven to boost channel mobility and offer considerable scalability potential. imec believes they show a possible evolution of the FinFET/trigate architecture for 7 and 5nm cmos technologies. "Unlike published Ge FinFETs, this work demonstrates a Ge-SiGe heterostructure based quantum-well device in a FinFET form, which not only provides strain benefits but also enhances short channel control," said programme director Nadine Collaert. In tests, the strained Ge p-channel FinFETs achieved peak transconductance values of 1.3mS/µm at VDS=-0.5V with short channel control down to 60nm gate length. Looking ahead, imec says future developments will focus on improving device performance through P-doping in the SiGe, optimising Si cap passivation thickness on the Ge, and improving the gate wrap of the channel. Aaron Thean, director of the logic R&D programme at imec, commented: "This new achievement, implementing Ge into the channel through our fin replacement process, is another key ingredient to our menu of process possibilities for monolithic heterogeneous integration to extend cmos and SOCs."