Imec develops FinFET flow
1 min read
As process technology continues to shrink, FinFETs are becoming more important, particularly in analogue circuitry and in srams, due to their short channel effect control and transistor compactness. Until now, fin height control and recess of shallow trench isolation (STI) oxide have remained challenges. However, Belgian research institute imec has developed a new trigate FinFET fabrication technology in which it has made 20nm wide fins at pitches ranging from 200nm to 90nm.
The process has been demonstrated in a 65nm technology node FET/FinFET cofabrication flow. The process flow uses two oxide field recess steps to achieve the target topographies – 50nm for FinFETs and flat for planar FETs. The results are said to indicate perfectly filled trenches, better fin height control and bulk FinFET static performance similar to that of planar cmos.
The process has been enabled using Applied Materials' Siconi selective material removal chamber. This allows silicon oxide to be removed in a controlled manner.
The dry oxide removal process is applied after trench etching and STI trench fill with oxide. In a sequence of steps, 20nm of oxide is removed in each step, giving a digital character to the etch process. Nitride is then removed in a hot phosphoric bath and the oxide field is recessed until the required fin height is attained.
According to imec, this method is more robust than conventional wet oxide etch, which can have undesirable results.
