imec partners with Cadence on 3d test tool

The solution, based on the latter company's Encounter Test technology, was verified on an industrial test chip containing a logic die and a JEDEC compliant Wide I/O mobile dram. It includes the generation of dram test control signals in the logic die and the inclusion of the dram boundary scan registers in the serial and parallel test access mechanisms of the 3d test architecture. The module has been validated on an industrial test chip, an interposer based 3d stacked ic which includes a silicon interposer base die, a 94mm² logic SoC in 40nm technology and a single Wide I/O dram rank. The validation results show that the silicon area of the additional DFT wrapper is negligible compared to the total logic die size (<0.03%). Moreover, the test pattern generation was said to be very efficient and effective. "This solution is another big step forward toward market introduction of 3d stacked ics for high performance, low power mobile applications," said Bassilios Petrakis, product marketing director for Cadence's Encounter Test product family. "Our collaboration with imec has enabled the creation of an industry leading solution that enhances efficiencies of 3d ic design for our customers."