RVVI provides a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation. The flexibility associated with RVVI supports the full range of RISC-V specifications and features that can be adopted with increasing levels of complexity for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, plus user-defined custom instructions and extensions.
RVVI supports RISC-V innovation with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects.
While RISC-V processor IP cores can be tested against the ISA (Instruction Set Architecture) specification, this is just the initial verification phase. The integration of the processor core must also be tested with the interactions across external peripherals and other system level components. By expanding the RVVI specification to include external components with a standards-based interface allows the reuse of components from the Open Virtual Platforms library of open-source models that are available.
Testbenches with RVVI compatible virtual peripherals can now be used to support RISC-V verification with system level testing of asynchronous interrupt and debug module events.
As a flexible framework, RVVI covers the needs of verification teams undertaking RISC-V processor functional verification and is a foundation for developing future guidelines, examples and verification IP. For more experienced DV engineers, RVVI offers the flexibility to cover the most complex verification challenges for advanced RISC-V designs. Some early supporters of RVVI include Codasip, NSITEXE (Denso), OpenHW Group, MIPS Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.
“All the significant progress in processor innovation can be traced back to two fundamental building blocks: Abstractions and Standards,” said Simon Davidmann, CEO at Imperas Software. “Simulation of the latest designs with billions of transistors is achieved through abstraction, similarly the success of IP reuse has been enabled by standards. Now the emerging RISC V verification ecosystem can build on the open standard RVVI flexible framework as a basis for verification IP and quality testing methods.”
