This solution includes Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D).
The tests are designed to extend the company's current range of tests for ratified and near-ratified specifications tests, and complement the de facto industry adoption of the Imperas RISC-V verification reference model.
Processor verification is the essential focus of any development team. Design bugs that are caught early help projects complete on schedule. The impact of late-stage bugs, and associated costs, can be significant.
The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog UVM environment. This covers asynchronous events and offers a seamless, time-saving, transition to debug analysis when an issue is found.
The ratified RISC-V specification defines the following standard extensions:
- 32F: 32bit Single-Precision Floating-Point (IEEE 754-2008 arithmetic standard)
- 32D: 64bit Single-Precision Floating-Point (IEEE 754-2008 arithmetic standard)
- 64F: 64bit Single-Precision Floating-Point (IEEE 754-2008 arithmetic standard)
- 64D: 64bit Double-Precision Floating-Point (IEEE 754-2008 arithmetic standard)
Suites totalling over 3.5 million instructions now available for free as open-source include:
- New Test suites for RV32F, RV64F, and RV64D ratified specifications
- Test suites for RV32/64IMC ratified specifications
- Test suite for RISC-V Vectors
Contact Imperas for spec version 0.9, 1.0 draft and other configs of xlen, elen, vlen, slen
- Test suite for RV32/64K Crypto (scalar) 0.8.0 draft specification
- Test suite for RV32/64B Bit Manipulation 0.93 draft specification
Coverage is a key aspect for any verification plan, as it helps measure the progress toward the quality targets for design completion and tape-out milestones. To support instruction and architectural functional coverage, the Imperas RISC-V golden reference model has been further enhanced with built-in monitors to provide coverage metrics without the need for post-simulation processing or other delays with log file analysis.
The free riscvOVPsimPlus RISC-V reference model and simulator, which has been widely adopted across the RISC-V verification ecosystem, supports the RISC-V ratified specifications for RV32/64 IMAFDC plus also the 'near-ratified' ISA extensions for Vector “V”, Hypervisor simulation “H”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions.
To support the SystemVerilog encapsulation of the reference model, the Imperas RISC-V Processor Verification IP (VIP) package includes example SystemVerilog supporting components and modules for interfacing and synchronization between the Imperas RISC-V golden reference model and the RTL core under test in a step-and-compare verification flow. This approach covers the important aspects of asynchronous events and debug mode operation while also supporting the DV engineer’s active investigation directly at the point of interest during test failure analysis and resolution.
Imperas offers Extendable Platform Kits (EPK) that are provided as source and includes the platform, models, scripts, and software to shorten the time to productivity. EPKs contain:
- An example platform for use with Google RISCV-DV Instruction Stream Generator flow
- An example platform for step-and-compare SystemVerilog encapsulation test bench
- An example platform for RISC-V functional coverage
RISC-V processor designers are pushing the boundaries of design innovation and dedicted floating point hardware can be one of the most demanding verification tasks,” said Simon Davidmann, CEO at Imperas Software Ltd. “The Imperas Floating-Point tests supports processor DV with instruction-based tests across the architectural envelope, and using a ‘step-and-compare’ flow with the Imperas reference model that covers asynchronous events with a seamless transition to debug and resolve issues.”
