RISC-V is an open standard ISA (Instruction Set Architecture) that allows any SoC developer to design and extend a custom processor, while remaining compatible with the growing ecosystem of supporting tools and software.
With ImperasDV, SoC developers will now have a dependable, reference model-based solution for verification that is compatible with the current UVM SystemVerilog methods for SoC verification.
Currently SoC verification accounts for 50-80% of the total design time and cost, however these estimates do not include the processor IP, since the base assumption is that specialist suppliers provide a pre-tested building block of sufficient quality.
With RISC-V, since any SoC team can now undertake the design freedom to implement a custom processor, optimised to the unique application requirements, they also have to assume responsibility for the extra complexity of processor verification. As a guide to the scale of the DV task, on average a processor core can be 10x the complexity of the SoC that is developed around it.
Due to the wide range of configuration options within the RISC-V specifications, the verification task has previously required extensive set-up and time-consuming manual adjustments to the established SoC design and verification flow. This is especially the case when custom extensions or modifications are included during the design, which are often iterated with the common HW/SW co-design as the software driven design style explores additional custom feature optimisations.
The increasing popularity of open-source IP is also contributing to the growth in teams undertaking verification as an in-coming quality inspection as part of initial phase of an SoC project, plus the design option to modify or extend the base core functionality will depend on a working DV framework from the start.
In response, ImperasDV has been created as a solution for easy, high quality processor verification adoption within the established SoC Design Verification (DV) flows based on UVM and SystemVerilog.
The key components are: Imperas RISC-V golden reference model, integrated test bench components, test suites, plus professional support and training.
The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog UVM environment. This covers asynchronous events and offers a seamless, time-saving, transition to debug analysis when an issue is found.
The ImperasDV RISC-V processor verification technology is already in active use with many customers, some of which have working silicon prototypes and are now working on 2nd generation designs.
“RISC-V is ideal for the latest compute requirements of single-core embedded controllers through to multicore arrays for high performance computing applications,” said Calista Redmond, CEO of RISC-V International. “Companies like Imperas are leading the charge in making SoC design and verification flow easier to further accelerate the mass adoption of RISC-V.”
“The open ISA of RISC-V is at the forefront of the wave of innovation that is stimulating design exploration across all embedded and compute markets,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V offers SoC develops the design freedoms for a custom processor as a unique solution optimized at the point of use, however this shifts the verification task from the few specialist suppliers to all SoC teams. Our new product, ImperasDV provides the efficiency and trusted quality for SoC teams as they step-up to the challenge of RISC V verification, which represents the greatest migration in verification responsibility in the history of EDA.”
