Industry's lowest power 40nm high bandwidth SerDes?
Analog Bits has announced what it claims to be the industry's lowest power 40nm, high speed Serialiser/Deserialiser (SerDes) IP. According to the clocking and interface IP specialiast, the macro is programmable to support multiple protocols and small enough to be used in embedded SoCs.
The device supports over 100 lanes, from 1 to 12.5Gb per lane on a single IC with a 5mw per Gb/s per lane power consumption. It is currently in production and is validated in industry standard protocols such as PCI Express, SATA and XAU.
Mahesh Tirupattur, pictured, executive vice president, Analog Bits, says the SerDes delivers the lowest chip to chip communications latency. "The new 40nm SerDes is ideal for high speed processors and consumer electronics devices in high definition tvs, set top boxes and game consoles," he said. "The IP's programmable features allow designers to use licensable IP to create highly differentiated SoC products while reducing design risk and speeding time to market."
The new SerDes interconnect is tested and currently available down to 40nm process geometries, with other nodes to follow.
