These controllers enable CPUs, GPUs and SoCs to utilise CXL interfaces to connect either DDR4 or DDR5 memory and in the process delivers more memory bandwidth per core, more memory capacity per core, and lowers the overall total cost of ownership in the data centre by allowing modern CPUs to optimise application workloads.
The SMC 2000 16x32G and SMC 2000 8x32G memory controllers have been designed to CXL 1.1 and CXL 2.0 specifications, DDR4 and DDR5 JEDEC standards and support PCIe 5.0 specification speeds. According to Microchip, the SMC 2000 16x32G is the industry’s highest-capacity controller with 16 lanes operating at 32 GT/s and supports two channels of DDR4-3200 or DDR5-4800. This results in a significant reduction in the required number of host CPU or SoC pins per memory channel.
Typical CXL attached memory modules include 512 GB of memory or more, providing an effective mechanism to increase the memory bandwidth available to processing cores and this enables data centre operators to deploy a broader range of ratios for memory to CPU cores depending on their actual application needs, resulting in improved memory utilisation and lower Total Cost of Ownership (TCO).
“This is our first CXL-based serial memory controller device to be introduced to the market,” said Pete Hazen, corporate vice president of Microchip’s Data Center Solutions business unit. “We identified CXL as a disruptive technology early on and were integral to the standard’s definition. Microchip’s continued presence in the memory infrastructure market underscores our commitment to improving performance and efficiency for a broad range of SoC applications to support the increasing memory requirements of high-performance data centre applications.”
“The CXL Consortium has the aim to deliver to the industry an open standard that accelerates next-generation data centre performance,” explained Siamak Tavallaei, president, CXL Consortium. “We’re pleased to see Microchip, a valuable contributor to the CXL Consortium, deliver a CXL solution enabling a new ecosystem for high-performance, heterogeneous computing.”
Microchip’s SMC 2000 CXL-based memory controllers employ a design that delivers Reliability, Availability and Serviceability (RAS) features delivering much greater levels of efficiency and performance. Through CXL connectivity, the SMC 2000 external memory controller enables a CPU or SoC to utilise a broad set of media types with different cost, power and performance metrics without having to integrate a unique memory controller for each different type. For example, using an SMC 2000 controller with DDR-4 memory, advanced CPUs that only directly support DDR5 can now also re-use DDR-4 memory expansion. The dual signature authentication and Trusted Platform support, secure debug, and secure firmware update ensure the SMC 2000 CXL-based controller family also meets all critical storage and enterprise application security needs.
The CXL platform is one of the biggest industry disruptions in recent years, bringing to market a new standard serial interface for CPUs to expand memory beyond the parallel DDR interface to provide the next level of efficiency and performance to the data centre.
