The Aeonic Power family debuts with two products: Aeonic Power HC, enabling energy optimisation of digital cores and logic blocks, and Aeonic Power LN to simplify power delivery for die-to-die interfaces (e.g. UCIe).
Aeonic Power HC is a high-current, on-die solution that delivers local, distributed power, enabling fine-grained DVFS for computational cores, clusters, and logic blocks. It has been designed to reliably supply core power to processing elements across a wide current range, helping SoCs balance performance and power, resulting in energy savings of up to 15%.
"Even with architectural innovations that are improving performance per watt, AI and HPC workloads are driving dramatic increases in total SoC power,” said Michael Smith, senior director SoC, Tenstorrent. “The industry is applying every available option to optimise power, and we believe that on-die voltage regulation will be invaluable in helping design teams take the next steps in energy-efficient computing by bringing fine-grained power management closer to computational cores."
Aeonic Power LN is built to support die-to-die interconnects in the chiplet ecosystem. Simplifying power distribution for D2D interconnects via on-chip regulation and reduction of inductive filters results in overall BOM improvements for chiplets.
“Power is a critical design parameter for large SoC design teams. While everyone wants more compute power, it comes at a significant cost at the chip, system and data centre levels,” explained Kevin Krewell, principal analyst, TIRIAS Research. “Movellus has a very interesting solution to the power challenge with their on-die voltage regulators that enable power management at a silicon block level, closer to each core. Design teams need every advantage to combat growing power demands, and Movellus offers a very valuable solution.”
The Movellus Aeonic Power family delivers a suite of power-focused telemetry, providing valuable insight into customers’ power delivery networks. These features will assist engineering teams with a data-driven approach to designing power networks and applying optimal silicon life cycle strategies.
“Power delivery is one of the most challenging areas in SOC design today,” said Mo Faisal, CEO, Movellus, “On-die voltage regulation holds tremendous potential to reduce power, simplify design, and increase the robustness of PDNs, but to date, only a handful of companies had the capability to tackle this using custom designs. Aeonic Power takes a new, scalable approach to on-die voltage regulation to make these solutions available to the broader market.”
The Aeonic Digital IP platform has been integrated by multiple customers and ported across various process nodes from 40nm to 3nm.
End applications range from ultra-low power edge AI devices to performance-centric cloud datacentre compute and AI offerings.
This latest milestone enables advanced on-die voltage regulation for high-performance SoCs and chiplets.
