Consequently, this means that both the sensor structure and its detection circuitry can be made at the same time within a chip using standard CMOS processes on whatever process node is required and, as a result, ASICs can now be made with several different sensors embedded within them.
This breakthrough in integration of sensor solutions as IP blocks will offer dramatic reductions in costs and size, according to Nanusens, as it completely replaces the current solution of discrete sensor packages.
“This is a major milestone for the company,” said Dr. Josep Montanyà, CEO of Nanusens. “The first was successfully making our nanoscale, sensor structures within the CMOS layers. This solves the problem that conventional MEMS have to be made on custom production lines that have limited production capabilities whereas we can make almost unlimited numbers of our sensors in CMOS fabs.
“These are available in standard packages such as LGA, QFN, WLCSP and others, but, like all other MEMS sensors, they require analogue circuitry to detect tiny capacitance changes coming from nano-displacements of their devices in operation. Our breakthrough is the creation of a fully digital detection circuit as this can be scaled down to the process node being used for the sensor structure and pairs to form a complete sensor and detection solution.
“Being able to shrink the pair simultaneously enables us to take advantage of all the benefits of using smaller CMOS geometries such as reduced costs and, importantly, reduced power consumption of more than 10x compared to analogue detection circuits. This is impossible for other MEMS sensor solutions as their structures cannot be shrunk neither can their analogue circuits as their transistors need a large area to maintain the required low levels of noise.”
The all-digital detection circuit provides a very fast on/off switching of the circuit of 3 microseconds compared to 300 microseconds or even several milliseconds in conventional analogue transconductance/charge amplifier circuits or similar.
This provides a significant advantage for applications requiring a very low sampling frequency, such as motion detector applications where the motion detector is typically used to wake up the rest of the device. If the device is in sleep mode most of the time, then the battery life is very dependent on the current consumption of the motion detector.
The ultrafast on/off of the new digital detection circuit results in sub micro-ampere current consumption on the 180nm test chip, which is much lower than the state-of-the-art in the market and more than doubles the battery life in these applications.
“This is a revolution for the sensor industry,” added Dr Montanyà. “Instead of being discrete packages on a PCB or a multi-die solution, all the required sensors can be integrated into an ASIC just like another IP block. This will provide a major reduction in the BOM, size and power requirements of many, multi-sensor devices, especially portable ones such as smart phones, ear buds, and smart watches. We are already in discussion with companies who want to license this IP.”
