Pioneering technology halves power consumption in electronics

The Silicon Valley based company, previously in stealth mode, claims it has managed to tackle the problem of power consumption reduction in tablets, notebooks and smartphones by addressing the physics behind transistor variation. According to SuVolta, its PowerShrink platform minimises the electrical variation of the millions of transistors on a chip – the primary cause of excess power consumption. By redefining the planar, bulk cmos transistor and related circuits, SuVolta researchers, led by cto, Dr Scott Thompson, radically lowered the power consumption without the need for new fabrication equipment or design infrastructure. "This last point is key," said Thompson. "When you move away from planar, bulk cmos, you're asking the semiconductor industry to bear a huge cost burden, literally billions of dollars, associated with developing new manufacturing facilities and circuit designs. SuVolta's technology works within existing designs and IP flows, and with existing equipment." SuVolta licenses its technology to semiconductor companies, with Fujitsu Semiconductor Limited being the first to publicly commit to the technology. Compatible with existing fabs and design flows, it enables semiconductor products to run for twice as long with the same total energy consumption, while not requiring changes to the existing semiconductor design and manufacturing infrastructure. SuVolta expects the PowerShrink platform to be in production in 2012.