Offering a combination of power and area efficiency for next-generation applications, the 112G XSR/USR PHY is an enabler of chiplet and CPO architectures for data centre, networking, 5G, HPC and AI/ML applications.
"Chiplets are already entering mainstream markets to enable cost-effective, high-performance products and to maintain signal integrity across variable physical distances,” said Shane Rau, research vice president, computing semiconductors at IDC. “SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity.”
The accelerated trend of disaggregation of large SoCs into multiple smaller chiplets demands faster time to market, yield improvement and design flexibility and the Rambus 112G XSR/USR PHY is being described as a critical enabler of the D2D and D2OE interconnects for chiplet architectures.
Implemented on TSMC’s advanced process technology, this chiplet connectivity solution has been demonstrated in silicon and has exceeded the challenging reach/BER performance of the CEI-112G XSR specification, and supports NRZ and PAM4 signalling at various data rates for maximum design flexibility.
“We’re pleased with the availability of Rambus’ PHY on our N7 process technology to address the growing market need for low-power, high-performance chiplet architectures,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “Our ongoing partnership with Rambus ensures that designers can meet next-generation requirements for performance and power efficiency in computing, AI/ML and networking using TSMC’s advanced process technologies.”
Leading-edge applications moving to chiplet architectures include next-generation 51.2 Terabit per second (Tbps) ASICs for network switches, where 112G XSR links will connect the digital switch ASIC die to CPO engines. In AI/ML and HPC SoCs, the 112G XSR PHY can be used to bridge purpose-built accelerator chiplets for natural language processing, video transcoding and image recognition. Another popular use case is the die disaggregation of large SoCs, hitting reticle size limits for manufacturable yields, into multiple smaller die connected using XSR links over organic substrate. Increasingly, these advanced applications are implemented on TSMC’s N7 process.
“This important milestone highlights Rambus’ leadership in high-speed SerDes enabling the industry’s highest value and most demanding applications,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “At an industry-leading power efficiency of sub-picojoule per bit, and unidirectional bandwidth approaching two terabit per second per millimeter, we are very proud to offer our 112G XSR/USR solution in partnership with TSMC.”
