The collaboration will support the Rapidus 2nm gate-all-around (GAA) process and leverage the design and manufacturing benefits from its backside power delivery network (BSPDN) technology to provide design solutions and IP portfolio to customers.
As the semiconductor industry struggles to keep up with significantly increasing design challenges driven by the need for more computation, GAA and BSPDN manufacturing technologies are becoming vital to meet increasingly stringent power, performance and area requirements.
Rapidus and Cadence are working to develop an AI-driven digital and analogue/mixed-signal reference design flow that includes Cadence design solutions.
Customers will be able to use Cadence's extensive portfolio of interface and memory IP components, including HBM4, 224G SerDes, PCI Express 7.0 and more, while also taking advantage of 2nm GAA and BSPDN design and manufacturing solutions that support Rapidus' Design for Manufacturing and Co-Optimisation (DMCO) concept.
“Our broad collaboration with Rapidus for 2nm GAA BSPDN technology leverages Cadence’s AI-driven solutions to solve real-world problems and meet customer needs,” said Dr. Anirudh Devgan, president and CEO at Cadence. “By bringing together Cadence’s advanced interface and memory IP technology, reference flows and Rapidus’ process technology, we're empowering the buildout of the AI infrastructure of tomorrow.”
“Our collaboration with Cadence on 2nm BSPDN technology puts us at the industry’s forefront, marking a major leap in semiconductor innovation for performance and efficiency. By combining our expertise, we're excited to set new technology standards and create transformative solutions for our mutual customers and the industry,” added Dr. Atsuyoshi Koike, CEO of Rapidus.
