Pushing processor power

Europe's contribution to high performance computing will be one of the highlights at this year's International Solid State Circuits Conference (ISSCC), the leading event of its kind. Engineers from IBM's Boeblingen facility in Germany will be providing more details on the company's POWER7 processor, which is aimed at high end servers. The highly parallel and scalable processor contains eight cores and can support four threads per core. Fabricated on a 45nm silicon on insulator process, the device comes with 32Mbyte of embedded dram and implements level 3 caches. The chip's designers have also included flexible voltage and clock domains to allow performance and power consumption to be optimised for any given application. Analogue design is always an interesting part of the ISSCC's proceedings. Issues that are usually explored include how to take advantage of the advances enabled by Moore's Law. Analogue has always lagged a few generations behind the leading edge, with the 'sweet spot' often claimed to be 0.25µm. But papers being presented this year imply that the real world functionality of analogue circuit techniques – sensing, signal processing and driving – can now be accomplished in the same technologies that enable the latest digital processors. These developments may enable advanced on chip analogue functions to be created that were previously thought to be out of the question. For the consumer this will mean more functionality, longer battery life and lower cost, particularly in portable devices. Session 4 will concentrate on this area. Presenters from the University of Pavia and from the Delft University of Technology will describe high speed mosfets that use chopping to remove low frequency imperfections. Although not a new technique in itself, the technique has been improved to the point where errors can be as low as 1µV. Meanwhile, power handling improvements will be described by Texas Instruments, which has developed a 45nm speaker driver capable of delivering 0.5W into an 8O load. Multicore processors are now in the mainstream, providing increased performance at lower power consumption. But as multicore complexity rises, so too does the need for more capable on chip communications. This year, innovations in networks on chip will be described at the architectural and circuit levels, improving computing performance through higher energy efficiency and throughput. Sun engineers will outline the multistage crossbar in its 128 thread Rainbow Falls 'datacentre on a chip'. This enables core to L2 communication at 461Gbyte/s. Meanwhile, Intel will present a ring interconnect bus that allows data to be passed at rates of up to 1.2Tbyte/s between eight Xeon cores. The company will also present a message passing scheme using on chip shared memory in a 48 core system. Dynamic voltage and frequency scaling in eight voltage and 28 frequency domains yields a network efficiency of 0.2Tbyte/s/W. Meanwhile, a collaboration between the University of Tokyo, Mitsubishi Paper Mills and the Max Planck Institute has realised User Customisable Logic Paper, said to allow ics to be generated using a standard ink jet printer. Basic logic blocks are prefabricated using 2V cmos organic transistors on a thin plastic film. The film is covered with a paper on which interconnects are drawn by a standard ink jet printer using a nanoparticle based ink that is conductive at room temperature. In the future, the collaborators believe, this type of technology will have wide application. ISSCC, the International Solid State Circuits Conference, takes place in San Francisco from 7 to 11 February. For more information on the event, click here.