Using the foundry’s latest processes, the design kit supports Siemens’ Calibre DesignEnhancer software solution, which is the latest addition to its Calibre nmPlatform for IC verification.
Unveiled earlier this year, the Calibre DesignEnhancer solution provides multiple use models that perform automatic layout optimisations to improve power robustness and reduce design cycles during design implementation. It works with the Samsung PDK to help mutual customers achieve substantial first-pass gains in designer productivity when compared to traditional place-and-route (P&R) processes, which often require design teams to conduct multiple runs to achieve the same Calibre nmDRC-correct results.
“Samsung Foundry has a long and successful track record of leveraging Siemens’ Calibre software to provide our customers with ‘Calibre nmDRC-correct’ designs. Based on the results we have seen, the Calibre DesignEnhancer solution provides them with a step function increase in via insertion efficiency, and faster turnaround time compared to classic approaches to the problem,” said JoongWon Jeon, Distinguished Engineer of Foundry Technology Development Team at Samsung Electronics.
The Calibre DesignEnhancer via insertion use model automatically inserts additional Calibre nmDRC-correct vias into layouts to reduce resistance that can minimize both voltage (IR) drop and electrostatic discharge (ESD) events in IC designs and, via optimisation, the use model can add up to millions more vias than previously possible.
“The incorporation of the Calibre DesignEnhancer solution with Samsung Foundry’s most advanced processes demonstrates what can be possible when world-class IC EDA and fabrication players partner to help mutual customers successfully and efficiently fabricate new devices in leading-edge technologies,” said Michael White, senior director, Physical Verification Product Management, Siemens Digital Industries Software.
