Today’s electronic devices require sophisticated, computationally intensive signal processing algorithms in order to execute audio, voice, vision, image, and communications processing functions. CEVA’s portfolio of signal processing cores and platforms are claimed to be tailored to enable these processor-intensive functions with minimal power consumption, suiting them for smart, connected devices.
UltraSoC’s universal debug solution is said to enable SoC developers to build an on-chip monitoring, control and communications architecture that is said to ‘look inside’ the chip while the device is operating. This assists the identification and elimination of bugs, speeding time to market. It can also be used after deployment for in-field performance monitoring and troubleshooting, leading to enhancements for current and next generation products.
Moshe Shahar, director of DSP Systems Architecture at CEVA, said: “As SoCs increasingly utilise multiple processors, the level of complexity rises accordingly and being able to monitor and analyse the behaviour of an entire device represents a distinct advantage for developers.”
The platform is said to consist of a dual core ARM and CEVA based system in an FPGA, running side-by-side, with the UltraSoC IP, effectively allowing the two processors to be debugged and fine-tuned within a single environment.
Rupert Baines, CEO of UltraSoC, added: “By working together, UltraSoC and CEVA now offer significant benefits to SoC developers who are designing CEVA DSPs into the next generation of emerging smart and connected devices.”
