DSP core supports transition to SoC based designs

• CEVA-X1643 builds on the CEVA-X family of dsp cores, by adding: support for an advanced data cache and tightly coupled memory architecture • memory management support a integrated power scaling unit • configurable 64/128bit AXI system buses • inherent support for seamless migration from TI C6x C code • 1GHz dsp performance using standard 40nm process technology, and • compatibility with other CEVA-X products. "Building on our CEVA-X family, the CEVA-X1643 offers a new level of performance to enable vendors using standard dsp based chips and assps to move to more flexible and cost effective core based SoC designs," said Eran Briman, CEVA's vp of marketing, pictured. "The dsp's advanced data cache architecture and software development environment dramatically simplifies the migration of legacy code to the CEVA-X architecture, enabling true, all in C programming." The CEVA-X1643 dsp features a very long instruction word (vliw) architecture combined with single instruction multiple data (simd) capabilities. Its 32bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle and 16 simd operations per cycle. A power scaling unit (psu) provides advanced power management for both dynamic and leakage power. The core supports multiple clock sources and power domains associated with the main functional units, such as the dsp core and the instruction and data caches. It supports multiple operational modes ranging from full operation, debug bypass, memory retention, to complete power shut off. According to CEVA, the core offers significant energy savings for both battery operated and stationary devices.