According to Socionext, by leveraging the eFPGA it can deliver a reprogrammable ASIC that can be reconfigured after tape-out to adapt to new requirements and changing standards and protocols as needed.
By integrating the FPGA, Socionext said that it will be able to improve performance and reduce power by eliminating one chip in the base station. This also delivers personalisation benefits to carriers who no longer need to share their proprietary software with the ASIC provider in order to have it added to the FPGA.
“While wireless base stations have always used FPGAs to provide carrier personalisation and upgradability, the demands of 5G require higher performance while reducing system power and cost,” explained Yutaka Hayashi, VP of Socionext’s Data Center and Networking Business Unit. “This can be achieved by using an ASIC solution and by leveraging Flex Logix’s eFPGA in that design. Now that the ASIC becomes reconfigurable, it enables our wireless customers to deliver a flexible 5G platform that can support carrier specific requirements today and in the future.”
"With a continuing need for more performance through hardware acceleration and lowering system power and cost, we’re seeing growing need for RTL reconfigurability within ASICs to support end-user specific customisation and acceleration,” added Geoff Tate, CEO of Flex Logix. ”Wireless base stations in particular are perfectly suited to take advantage of this flexibility."
EFLX is a digital architecture for development of embedded FPGAs for integration into SoCs, ASICs and MCUs of a wide range of sizes. The EFLX4K Logic IP core has 4K 4-input-equivalent-LUTs, 632 inputs and 632 outputs and is a complete eFPGA. The EFLX4K DSP IP core replaces about ¼ of the LUTs with 40 multiplier-accumulators for DSP and artificial intelligence (AI) applications. The two EFLX4K cores can be tiled together to make larger arrays to support applications needing more LUTs as required, well over 250,000 LUTs with any mix of Logic and DSP cores.
The EFLX arrays are programmed using Verilog or VHDL; and the EFLX Compiler takes the output of a synthesis tool such as Synopsys Synplify and does packing, placement, routing, timing and bitstream generation. The bitstream, when loaded into the array, programs it to execute the desired RTL.
