Interface ESD protection in the most advanced FinFET technology is challenging: ESD sensitivity is very high while conventional ESD solutions are not effective anymore. Sofics’ proprietary clamps are now proven in silicon to protect FinFET circuits against ESD events.
“Thanks to our close collaboration with TSMC through its Open Innovation Platform (OIP) IP alliance, Sofics engineers transferred our proprietary ESD and I/O portfolio to TSMC’s 3nm process technology earlier this year, this includes novel clamps that outperform reference solutions by reducing the clamp area by 66%,” said Koen Verhaege, Sofics’ CEO.
TSMC customers can leverage Sofics’ solutions to enable higher circuit performance, higher robustness and to reduce design time and cost of SoC design.
“SoC and chiplet designers need custom analogue I/O or ESD cells for applications including high-speed or wireless interfaces, low power, 3D packages or high voltage tolerant pads. Custom silicon proven ESD cells create distinct recurring value in any advanced technology,” said Verhaege.
Key aspects for the Sofics’ ESD solutions include legacy voltage tolerance, ultra-low leakage, small area and low parasitic capacitance. The IP can be used to protect the most sensitive core interfaces against Electrostatic Discharge. There are solutions for various voltage domains and interface types.
