This starts with a suite of IP blocks for general SoC management to control start-up of devices, clock and reset control and power domain handling. The SoC Management Suite has three components – the PMU (Power Management Unit, the URG (Universal Reset Generator) and the UCG (Universal Clock Generator).
Commenting Oliver Jones, Sondrel’s CEO, said, “For years, we have been creating IP blocks for our internal use when we design custom chips. We are now making these available for licensing by third parties. They are silicon proven as we have already successfully used them in designs for our customers.
“We had to create these IP blocks as there was nothing commercially available to deliver the functions and performance that we required for the advanced ultra-complex custom chips that we design. Some are slightly unusual but that is the very reason why we created them. If we needed them for a design, then others will too.”
The Power Management Unit (PMU) is used for:
- Managing the start-up of the SoC and bringing the SoC out of reset.
- Providing software control to allow any switchable digital domains to be powered up and down.
- Providing software with control over the reset tree (once start-up is complete).
- Managing system faults (including taking mitigating action as required and acting as the Error Detection Unit).
- Generating the system response to functional safety faults detected in the system. Such as putting the system into ‘Safe-Mode’.
The PMU can interact with a URG to control the resets via Sondrel’s Power Down Controller Interface control bus.
The Universal Reset Generator (URG) is an SoC IP that is responsible for coordinating on-chip reset management. The main purpose of this IP is Reset-tree management for the increasing complexity of logic within an SoC. It is intended to be lightweight and scalable so that it can be used across different types of SoC.
A typical SoC would employ at least one URG IP instance, while a multi-power-domain SoC or implementation requiring more distributed reset control, could have multiple instances depending upon the reset tree management requirements.
The URG goal is to have a single, generically configured block which will support the correct sequencing of resets to the whole system.
According to Sondrel, events that would change the state of the resets can come from several sources:
- A hardware trigger. Examples include: a system reset pin, a watchdog timer IP, a security IP, a CPU exception flag
- A software-driven event. i.e. a driver deciding that IP is in an unknown state.
- The Power Management Unit, which must manage resets in tandem with power island voltage controls to facilitate power state transitions.
The Universal Clock Generator (UCG) is an SoC IP that is responsible for coordinating on-chip clock management. It is intended to be lightweight and scalable so that it can be used across any scenario. It supports:
- Multiple clock sources and references as input to a generic crossbar.
- Up to 128 clocking channels which can be independently software configured.
- Clock dividers on each channel and a clock enable (glitch-free implementations).
- Observation clocking points.
- DFT (Design For Test) control of clock outputs.
Safety mechanisms such as detecting if a default clock has failed and indicating the fault to the system.
