Sunburst Chip Design repository for secure MCU development released

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lowRISC C.I.C., the open silicon ecosystem organisation, together with SCI Semiconductor, a leading developer of CHERI solutions, have announced the release of the open-source Sunburst Chip design repository.

New chip design repository ensure secure MCU development Credit: MarkD - adobe.stock.com

Both companies are CHERI Alliance founding members and this announcement is being described as a key milestone in phase two of the DSbD/UKRI-funded Sunburst Project.

The announcement marks a significant step in bringing CHERIoT-Ibex based secure microcontrollers to market, as leveraged by SCI’s ICENI device family, which will reach first commercial availability later this year.

Memory safety vulnerabilities account for around 70% of reported exploits, causing a growing number of industries from automotive to IoT and industrial systems to require secure, efficient microcontroller solutions that balance performance, power consumption, and affordability.

CHERI technology was developed to provide a critical solution that looks to address these vulnerabilities by enforcing memory safety at the hardware level.

“By addressing security challenges in a ‘by design’ manner, CHERIoT-Ibex has proven its potential as a next-generation secure microcontroller architecture. However, to move the needle, CHERIoT-based IP must be both commercial-grade and readily available,” said Dr. Gavin Ferris, CEO of lowRISC. “Our release, with SCI, of the permissively licensed open-source Sunburst Chip repository is a significant turning point in bringing CHERI-based security to the embedded systems market and represents a core deliverable of the Sunburst project.”

This announcement follows lowRISC and SCI Semiconductor’s commitment to tape out the Sonata design (incorporating Microsoft's Ibex-based CHERIoT core) which builds on the first phase of the Sunburst Project, which introduced CHERI technology to embedded engineers through the Sonata FPGA board and RTL platform.

The project was subsequently extended to deliver an open source SoC top-level, reusing much of the IP developed for OpenTitan ‘Earl Grey’, which itself has reached production with Google and is heading into Chromebooks this year.

Sonata platforms distributed to key stakeholders by the Sunburst project are driving awareness, technical engagement and innovation around memory-safe microcontrollers.

SCI Semiconductor is leveraging the Sunburst Chip repository as the foundation of their ICENI family of secure microcontrollers. As part of this effort, SCI is targeting a 22nm commercial process and will drive this design to form the basis for the first ICENI secure microcontroller, a commercial chip available in the second half of 2025.

“The availability of commercial-grade CHERI technology is a key factor in shaping the future of secure computing,” said Haydn Povey, Chief Executive, SCI Semiconductor. “We are on a mission to ensure that the market has access to robust, open-source foundations for secure-by-design microcontrollers enabling a focus on differentiation, just as we have with Iceni.”

The Sunburst Chip repository is now publicly available on GitHub. Use the link below to access it.

Developers and researchers are encouraged to explore the repository and leverage the technology for their own CHERIoT-Ibex based designs. For those looking to experiment with CHERIoT-Ibex, the Sonata™ low-cost boards are available to purchase via Mouser.

  • The CHERI Alliance is a community interest organisation promoting the global adoption of the Capability Hardware Enhanced RISC Instructions (CHERI) security technology across the computing industry. Building on over a decade of pioneering research by the University of Cambridge and SRI International, CHERI introduces a proven architecture designed to enhance system security through fine-grained memory protection and software compartmentalisation. The Alliance is actively engaging with industry, academia, and the public sector to standardise and implement CHERI across a diverse range of computing platforms.