The range of memory IP is intended to help speed up design times for customers as Paul Wells, sureCore’s CEO explained.
“Customers invariably want a certain amount of customisation to precisely fit their project’s needs. However, we have found that certain memory configurations keep coming up time and again because similar projects will have the same memory requirements.
“We have therefore productised these to become off-the-shelf IP that are immediately available to just be dropped into designs such as wearables, hearables, edge-AI and IoT where ultra-low power consumption is vital for competitive differentiation and hence to the success of the end product.”
Wearables and hearable devices typically require a long battery life and an “always-on” listening mode. A suitable solution is sureCore’s EverOn single port SRAM that has an ultra-wide operating voltage range from 0.6V to process-nominal voltage – this has been adopted by both smart watch and “True Wireless Stereo” (TWS) earbud developers.
Standard memory designs can only work down to process-nominal voltage however EverOn’s unique banking structure allows architects to implement fine-grained, even lower voltage, sleep modes for up to 50% power savings compared to standard memory cells.
Consequently, the voltage of the chip can be dynamically adjusted up and down in tandem with the performance requirements for the operation in hand to save power as required. For example, this could be going from a high performance to a low performance mode or even a monitoring state awaiting a wake-up event.
Front end views are available in sureCore’s web-based compiler to help facilitate customer evaluation. Versions for 40ULP, 28HPC+, 22ULL are available with memory instances up to 0.5MB supported.
Another important group of applications include Edge-AI, Machine Learning and also hearing aids that need to maximise battery life by minimising both operating and stand-by power consumption.
To address these applications sureCore’s PowerMiser is an ultra-low dynamic power, single port SRAM that delivers, according to sureCore, up to 50% dynamic power savings compared to market leaders in addition to an average 20% saving on leakage power.
PowerMiser’s patented “Bit Line Voltage Control” techniques have the added benefit of virtually eliminating performance compromises even with a reduced power envelope. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are available. Various periphery Vt options are possible in order to optimise for either leakage or speed as demanded by application need.
Front end views are available in sureCore’s web-based compiler to help facilitate customer evaluation. Versions for 28HPC+, 22ULL, 16FFC and 28FDSOI are available with memory instances up to 0.5MB supported.
