According to SureCore, a developer of ultra-low power memory solutions, cutting the supply voltage to logic can deliver dramatic power savings, however developers face a problem in that the embedded SRAM cannot be operated at this reduced voltage.
Edge-AI applications must provide significant inferencing power whilst still delivering acceptable battery life.
In response, SureCore has created a new range of ultra-low voltage SRAM solutions, called PowerMiser Plus, that can operate down to 0.45V, enabling customers to create low power products. Because both the logic and memory can interface at the same voltages, they can be adjusted in tandem to increase and decrease performance and therefore power consumption simultaneously as required by the application.
PowerMiser Plus has already been licensed to two customers in the edge-AI space. For one customer, sureCore ported the PowerMiser Plus architecture to a 12nm process interfacing to logic operating at 0.45V whilst delivering 400MHz performance at the worst-case corner. The SoC had an on-chip LDO generating both the logic supply as well as a 0.65V supply for the SRAM storage arrays. This ensured that as system level shifts in operating voltage were made so as to meet the required performance targets, then the two supplies tracked each other within a predefined margin. This meant that the use of power-hungry level shifters within the SRAM were avoided, thereby further optimising power consumption.
For another edge-AI customer, the PowerMiser Plus architecture was optimised to provide an ultra-low voltage, single port solution that took advantage of the low voltage profile of the foundry high current bit cell. Whilst operating at 0.6V nominal and delivering 400MHz worst case, the memory was also characterised to operate at 0.5V providing dramatically extended battery life.
Paul Wells, sureCore’s founder and CEO explained, “More and more customers are responding to market pressures to deliver extended battery lives. In doing so, they can no longer ignore the significant power drain of their embedded SRAM. This is especially true in the edge-AI space where pattern matching requires heavy SRAM usage.
“Key to delivering the power savings demanded is the wholesale shift of the application to a lower operating voltage which is fine for the logic, of course, which can still deliver relatively high performance. Memory is a different matter entirely and needs very special attention. With our patented power saving technology and low voltage expertise, we are able to craft the PowerMiser Plus architecture. This successfully delivered the low voltage solutions needed by our customers enabling them to hit their challenging power targets.”
