As the requirements for increased bandwidth to support video-on-demand, social networking and cloud services continues to rise, Synopsys VC VIP for Ethernet 800G, based on the Ethernet Technology Consortium (ETC) specification, will enable system-on-chip (SoC) development teams to design next-generation networking chips for data centres faster, resulting in accelerated verification closure and time-to-market.
The VC VIP is used to verify Synopsys' DesignWare 56G Ethernet, 112G Ethernet, and 112G USR/XSR PHYs for FinFET processes, which designers can integrate into 800G SoCs to address long reach and short reach interface requirements.
The ETC standard provides specifications for an 800G implementation based on 8 lane x 100 Gb/s technology, enabling adopters to deploy advanced high bandwidth interoperable Ethernet technologies.
"Our 800 Gigabit Ethernet Core will help customers create flexible system solutions for 800 Gigabit Ethernet applications," explained Francois Balay, president of MorethanIP. "Being first in the industry, Synopsys VIP, source code test suite, and DesignWare IP for Ethernet 800G will help to strengthen the ecosystem and facilitates early adoption of the technology and fast development of high-speed networking applications."
Synopsys VC VIP for Ethernet uses a native System Verilog UVM architecture, protocol-aware debug and source code test suites and can switch speed configurations dynamically at run time and includes an extensive and customisable set of frame generation and error injection capabilities.
In addition, source code UNH-IOL test suites are available for key Ethernet features and clauses, allowing teams to quickly jumpstart their own custom testing and accelerate verification closure.
- Synopsys VC VIP and source code test suite for Ethernet 800G are both available today as early access standalone products. The DesignWare 56G and 112G Ethernet PHYs are available now. The silicon design kit for the DesignWare USR/XSR PHY IP in 7nm FinFET process is available now.
