Intended to address the broader range of power, performance and area (PPA) demands of embedded applications and based on the same VLIW/SIMD architecture as the company's higher performance 512-bit ARC VPX5 DSP processor, these additions are able to deliver up to two-thirds lower power and area.
The ARC VPX DSP IP family now provides greater flexibility for designers to optimise their designs based on the power, performance and area (PPA) requirements of embedded workloads such as IoT sensor fusion, radar and LiDAR processing, engine control, voice/speech recognition, natural language processing and other edge AI applications.
"AI-enabled devices have an increasing need for specialised processors that can handle a variety of DSP and machine learning workloads with a high degree of energy efficiency," said CL Chen, COO at Neuchips, an AI domain specific compute solutions startup in Taiwan. "By expanding the ARC VPX processor family to support a range of vector lengths, Synopsys enables designers targeting a broader set of applications to implement high-performance signal processing in their designs."
The ARC VPX2 and VPX3 DSP processors are available in single- or dual-core configurations to address a broad range of application requirements. Each VPX core contains a scalar execution unit and multiple vector units that support 8-bit, 16-bit and 32-bit SIMD computations.
The VPX DSPs support half-, single-, and double-precision floating point formats, and up to three floating point pipelines are available in each VPX core. T
According to Synopsys, the unique hardware acceleration for special math functions used in linear and non-linear algebra functions deliver high-precision results.
The VPX DSPs include enhancements to the instruction set architecture (ISA) and load/store bandwidth to deliver up to twice the performance of existing offerings for common DSP functions such as fast Fourier transforms (FFTs).
In addition, the safety-enhanced ARC VPX2FS and VPX3FS integrate hardware safety features including error correction code (ECC) protection for memories and interfaces, safety monitors and lockstep mechanisms that help designers achieve the most stringent levels of ISO 26262 ASIL B, ASIL C and ASIL D functional safety compliance.
As with other Synopsys ARC processors, the VPX2 and VPX3 processors are supported by the Synopsys ARC MetaWare Development Toolkit, which provides a vector length-agnostic software programming model specifically optimised for the VPX hardware architecture.
