Synopsys ARC-V Processor IP includes high-performance, mid-range, and ultra-low power options, as well as functional safety versions, to address a broad range of application workloads.
To help accelerate software development, the Synopsys ARC-V Processor IP is supported by the Synopsys MetaWare Development Toolkit that generates highly efficient code. In addition, the Synopsys.ai full-stack AI-driven EDA suite has been co-optimised with ARC-V Processor IP to provide an out-of-the-box development and verification environment that helps boost productivity and quality-of-results for ARC-V-based SoCs.
“The global adoption of the open-standard RISC-V ISA is defining the future of semiconductor design, and it’s through the commitment and advancements from technology innovators like Synopsys that RISC-V continues to accelerate the future of computing,” said Calista Redmond, CEO, RISC-V International. “Synopsys ARC-V Processor IP, combined with the company’s co-optimised EDA and verification solutions, contribute to greater flexibility and choice in the RISC-V ecosystem for the benefit of chip design across industries.”
Synopsys has delivered multiple generations of power-efficient, highly scalable ARC Processors and said that it was looking to expand the portfolio to support the RISC-V ISA. With ARC-V IP, Synopsys is delivering ultra-configurable, extensible processors that enable developers to differentiate their SoCs and optimize for the best power, performance, and area (PPA) balance.
“RISC-V processors are gaining in popularity as more designers look for greater design flexibility and more options,” said John Koeter, senior vice president of product management and strategy for IP at Synopsys. “Our ARC Processor IP portfolio provides a wider choice for customer processing needs based on the proven, scalable RISC-V ISA to help them meet their diverse workload requirements.”
Synopsys ARC-V Functional Safety (FS) Processor IP has integrated hardware safety features to detect system errors, support ASIL B and ASIL D safety levels, and accelerate ISO 26262 functional safety and ISO 21434 automotive cybersecurity qualifications and has been developed on Synopsys’ ISO 9001-certified Quality Management System (QMS), enabling designers to meet challenging ASIL D systematic development standards. In addition, the MetaWare Development Toolkit for Safety helps software developers accelerate the development of ISO 26262-compliant code.
Synopsys can offer a variety of tools and technologies to accelerate the design and verification of SoCs using its RISC-V ARC-V Processor IP, including:
Synopsys.ai, a full-stack AI-driven EDA suite that leverages the power of AI from system architecture through manufacturing to optimize PPA and speed time to market;
Synopsys Fusion QuickStart Implementation Kits, which offer scripts, reference guides, and a baseline floorplan to help customers maximize PPA for ARC-V based designs;
Synopsys verification solutions, including architecture design for system-level analysis and optimization of power and performance, virtual prototypes with Synopsys ARC-V models, hardware-assisted verification, and verification IP to speed verification and software development, and;
Synopsys Cloud SaaS platform with browser-based access to unlimited EDA licenses, pre-optimised compute, and complete license management automation, enabling designers to deliver higher quality chips ahead of schedule.
Synopsys has also announced that it has joined the RISC-V International Board of Directors and Technical Steering Committee to support industry adoption of the RISC-V instruction set architecture (ISA) and participate in defining the future of computing architecture standards.
