Paul Cunningham, vp of R&D, noted: "The productivity gap is widening and there has been a call to action to develop evaluation tools which boost productivity dramatically. If we're serious about closing this gap, we have to target a number of things."
Genus features a massively parallel architecture, enabling physically aware context generation, unified global routing and power, performance and area optimisation at a global analytical architecture level.
Cunningham said that, while physical aspects of chip design have been parallelised, the core part of the design flow involving timing optimisation hasn't been distributed. "We have done this by going in at the flow level so that any subset of a design can be cut out and sent to another machine. The data structure remains the same as the original and you can keep 'chopping' the design up."
He noted that, while certain parts of a design are critical and can't be cut across, this process needs to be done in a way that minimises the amount of data traffic. However, the result is said to be full timing and physical context for any element of the design.
The first level of distribution is at 100k instances or more, with timing driven across multiple machines and CPUs. The second level address blocks of around 10k instances, again across multiple machines and CPUs. Finally, there is algorithm level multithreading on one machine.
Cunningham said a 34million instance design – equivalent to more than 100m gates – took two days to run using 16 quad core CPUs.
Genus can also share the same data engine as the recently announced Innovus place and route package, with a common interface improving ease of use and designer productivity.
