Aimed at providing a cutting-edge, flexible, certified, Secure Enclave – eFPGA security IP solution the two companies are looking to leverage their combined expertise in embedded FPGA and secure hardware cryptography and are developing a solution for the market that is a response to the EU’s Cyber Resilience Act and the US’s Cyber Trust Mark.
The scope of applications covered by the solution includes SoC, HSM, Digital Authentication, and Aerospace.
This new combined security IP solution will provide increased functionality and cryptographic algorithm agility, enabling updating after tape-out and even in the field, to counter evolving cyber threats.
SoC manufacturers will benefit from much greater flexibility, and third-party software providers will be able to leverage the RISC-V CPU to facilitate software development. By adding an eFPGA core to the cryptographic engine, the TESIC-510 FPGA Secure Enclave IP provides a much higher level of security available through Common Criteria EAL5+ certified cryptographic libraries, coupled with algorithmic flexibility and performance.
“We are very enthusiastic about the new augmented solution that our collaboration with Menta will enable us to bring to the market. The innovative approach brings unique added value to chipset vendors. They can manage the security of their platform during the entire product life cycle, including in the field, while taking account of their end customers’ requirements,” commented Mikaël Dubreucq - Tiempo Secure’s VP Global Sales & Marketing.
“Our eFPGA-Secure Enclave solution is the best solution for our customers to de-risk cryptography for now and the future,” added Yoan Dupret, Menta’s Managing Director & CTO.
