The USB 2.0 IP is based on a patented hardware-based bare-metal technology that requires no software running to establish communication.
When combined with high speed USB 3.1 IP from Synopsys, it will allow engineers to gather high volumes of rich system performance data, with access from “cycle zero” on start-up. eUSB is also supported for access to devices designed on advanced process nodes.
The silicon-proven solution is designed to be both accessible and low cost. Based on USB standards there is no need for an expensive debug probe and it is compatible with any PC and can work with any development tool via a simple software driver.
It’s increasingly important for developers to be able to ‘look inside’ products at a system level to optimise performance, and debug problems.
This requirement extends throughout the product lifecycle, so where physical access to the electronics may be limited – developers need to gather large amounts of data via interfaces that are available within the product itself – usually the USB.
Combining Synopsys and UltraSoC’s solutions in this area provides a suitable solution for Synopsys users. Any debug and analytics interface is subject to two vital design requirements. First, the interface itself must be robust in the event of system failure: if the system software fails to boot at start-up or crashes irretrievably during operation, it must still be possible to access the internal analytics, diagnostic and debug capabilities.
This is the so-called “cycle zero requirement”. Second, the interface must be able to cope with the data rates generated within the system. CPU tracing capabilities and embedded monitors such as those provided by UltraSoC can generate large data sets which need to be moved quickly off-chip for analysis. This is an increasing problem as systems become larger and more complex. The combined UltraSoC / Synopsys solution looks to address both of these key requirements.
“The benefits of USB as a debug interface are well understood: in fact our customers tell us our solution is exceptionally robust,” said UltraSoC CEO Rupert Baines, ‘USB is readily accessible in products ‘off-the-shelf’ and does not require additional chip pins in order to provide high-performance access, unlike dedicated debug interfaces such as JTAG or proprietary high speed debug ports that require a dedicated interface and an expensive debug probe. It’s therefore an ideal interface for accessing analytic data from electronic products which increasingly require continuous monitoring and improvement throughout their lifetime.”
UltraSoC embedded analytics technology delivers analysis and monitoring of an SoC regardless of the CPU or architecture. UltraSoC’s embedded analytics covers all major ISAs including open source RISC-V and even mixed (heterogeneous) architectures and is fully compatible with all third party tools.
