As the first stage in the introduction of IP cores that meet the AMBA 4 AXI4 specification for interconnecting functional blocks in SoC design, Xilinx has released ISE Design Suite 12.3.
"Xilinx is the first to standardise on the AMBA 4 specification as part of our interconnect strategy to support 'plug and play' fpga design," said Vin Ratford, pictured, Xilinx' senior vice president of worldwide marketing. "The flexibility inherent in the AXI4 interconnect enables it to be tailored for performance and area, while making it easier for customers to integrate IP from different domains and IP providers. It also enables asic designers to migrate existing designs and IP to Xilinx fpgas."
The AXI4 protocol defines a point to point interface developed to address SoC performance challenges. It supports multiple clock domains, along with data up sizing and downsizing. The AXI4 specification also includes features such as address pipelining, out of order completion and multithreaded transactions.
According to Xilinx, deployment of the AMBA 4 AXI4 specification means designers will have a consistent way to interconnect IP blocks while enabling better use of design resources through the use and reuse of IP. ISE Design Suite 12.3 includes enhancements to the CORE Generator tool that accelerates design time by providing access to highly parameterized IP as well as the Xilinx Platform Studio and System Generator tools that enable designers to quickly configure their system architecture, buses and peripherals.
Xilinx's adoption of the AMBA protocol also provides designers access to established asic verification methodologies and existing AMBA protocol based IP, allowing designers to move to fpgas as a platform of choice.
