Xilinx adds partial reconfiguration to fpga design tools
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Xilinx has unveiled its fourth generation partial reconfiguration design flow and improvements to its intelligent clock gating technology, said to reduce dynamic block ram power consumption in Virtex-6 designs by 24%.
Partial reconfiguration allows an fpga to be 'repurposed' while operational without affecting other applications running on the device. It also power consumption to be managed by swapping out functions with high power consumption for more power efficient functions when the highest performance is not required.
An easier to use partial reconfiguration design flow is now supported in ISE Design Suite 12.2, which also allows designers to reduce power consumption and reduce overall system costs in Virtex-4, -5 and -6 devices. In addition, a low cost simulation solution for the embedded design flow is also included.
"As systems become more complex and designers are asked to do more with less, the adaptability of FPGAs, in addition to their inherent reprogramability, has become a critical asset," said Tom Feist, senior marketing director, ISE Design Suite. "Xilinx FPGAs have long supported partial reconfiguration and the flexibility to perform on-site programming and re-programming. Today, however, the severity of the constraints on cost, board space and power consumption requires exceptionally efficient and economic design strategies to compete, which is why we've made the design flow easier."
Meanwhile, Xilinx' Intelligent Clock Gating technology, acquired in 2009 from PwrLite, allows block ram power consumption to be reduced. A set of algorithms is used to 'neutralise' unnecessary logic activity. This can reduc overall dynamic power consumption by 30%.
Intelligent clock gating optimisation in ISE Design Suite 12.2 will also reduce power for dedicated ram blocks in simple or dual port modes.
