According to the company Platypus is the first, and currently only, commercial eFPGA IP product with:
- 100% open and standardised FPGA architectures
- 100% open-source FPGA bitstream formats
- 100% open-source FPGA development tools
Obsolescence is a critical issue for FPGA-based systems where lifespans can range from 10 to 50 years. For example, the F-35 fighter jet, which began in 1997 and didn’t enter full production until 2021, has seen transistor density increased by a factor of 10,000X, and the FPGA industry has introduced six new generations of architectures.
This mismatch between semiconductor advancements and slow infrastructure development cycles has led to an estimated $50–$70bn in obsolescence-related NRE costs for the US military alone, with the additional problem that 15% of all replacement semiconductor parts are counterfeit.
Since their introduction in the 1980s, commercial FPGA products have become increasingly complex, less standardised, and more opaque, which has exacerbated issues related to parts obsolescence and counterfeiting.
In the best case, an end-of-life notice for an FPGA device or eFPGA IP core necessitates a complete subsystem redesign. In the worst case, it may result in the termination of an entire program.
Consequently, the logical next step in addressing FPGA obsolescence and counterfeit problems is a move away from single source parts and to establish a set of open-standard FPGA architectures, similar to the successful standards created for memory and passive components.
There have been numerous attempts at opening up FPGAs. The Versatile Place and Route (VPR) open-source FPGA research platform was introduced in 1997, and that platform has helped lower the barrier to high-quality, reproducible FPGA research ever since. Unfortunately, VPR has remained solely a research tool, and there is still no fully open RTL-to-bits flow for commercial FPGAs.
To address the lack of fully open FPGA devices, DARPA funded the OpenFPGA and PRGA FPGA generator research projects in 2018. While these open-source generators facilitated the tape-out of several academic chips, the resulting designs were neither standardised nor commercialised and as FPGA complexity has surged there is still not a single open and standardised commercial FPGA product on the market.
With the launch of the Platypus eFPGA family, Zero ASIC is working to standardise FPGAs by openly releasing complete architecture descriptions and bitstream formats of its commercial Z1000 eFPGA IP under an open-source Apache License, with the goal of making it an open standard.
Historically open standards have proven to be a highly effective defence against obsolescence and predatory pricing strategies. Notable ubiquitous open hardware standards include the RISC-V ISA, IEEE Ethernet PHYs, JEDEC memories, passive footprints (e.g., 0603, 0805), PCIe, and USB. Just like with RISC-V, creating an open standard does not mean the implementation must be open source.
“Developing an open-standard FPGA architecture and an ecosystem of standard compliant components will revolutionise FPGA-based system design, much like RISC-V has transformed CPU design. Just like with RISC-V, market dynamics will dictate whether the potential upside of open standards overcomes the status quo inertia of vendor lock-in,” said Andreas Olofsson CEO and founder.
Platypus standard eFPGA IP cores are available today to early access customers while the FPGA Architect platform will be available to customers in Q2 2025 on a per project basis.
