As the industry rapidly transitions to 400GB and 800GB wired communication applications, 112G is a key building block necessary to support the ever-growing demand for more bandwidth in data centre and network applications, doubling the data rate of 56G SerDes.
Rambus claims to be at the forefront of implementing 112G design to address the long-reach backplane requirements for next-generation data-intensive applications.
This high-speed PHY provides the "optimal combination" of power efficiency, performance and area, adding to Rambus’ large portfolio of silicon-proven IP, design tools and reference flows. With the introduction of 112G, this technology achieves higher performance to rapidly enable industry infrastructure for the 400GB and 800GB applications.
The Rambus 112G LR SerDes PHY has been designed to deliver enterprise-class performance across the demanding backplane environments beyond 30dB. To achieve this data rate requires an innovative SerDes architecture approach to meet the ever-growing data needs for high-speed data-intensive applications.
Key features of the Rambus 112G LR SerDes PHY include a scaleable ADC-based (analog-to-digital converter) architecture with support for PAM-4 and NRZ signalling, and a DSP-based architecture for improved signal to noise ratio (SNR) and extended reach.
It is also configurable to provide power, performance and area (PPA) optimisation for medium reach (MR) and long reach (LR) applications.
