Engineering publications brought to you by Mark Allen

Risc v

Cadence and Imperas support NSITEXE in development of automotive RISC V Vector processor IP

Bluespec’S MCUX RISC-V processor enables implementation of custom instructions and accelerators

Green Hills Software provides enhanced support to Imagination’s RISC-V CPUs

Dolphin Design turns to Imperas for processor functional design verification

Semidynamics unveils fully customisable Vector Unit to go with RISC-V cores

Andes Technology unveils AndesAIRE product line

Esperanto Technologies running generative AI models on low-power RISC-V architecture

Semidynamics launches fully customisable RISC-V IP cores

Collaboration to accelerate RISC-V application software development

Arteris and SiFive to accelerate RISC-V SoC design of Edge AI applications

Imperas and Synopsys collaborate on SystemVerilog based RISC-V verification

QuickLogic and Andes Technology partner for eFPGA joint promotion