The ImperasDV RISC-V processor verification solution is fully compatible with the Cadence verification flow, including the Xcelium Logic Simulator and Verisium Artificial Intelligence (AI)-Driven Platform for debug, analysis and management.
ImperasDV is a RISC-V processor verification solution based on the lock-step continuous compare methodology that enables both accurate detection of issues and the efficient resolution of discrepancies between the design under test and the Imperas RISC-V Reference Model.
The Cadence Xcelium Logic Simulator provides the SystemVerilog simulation environment, including the tightly-integrated, high-performance interface required to work with ImperasDV effectively. These are used with the Cadence SimVision Debug and analysis tools to create a unified environment for comprehensive verification of the NSITEXE Akaria processor IP, including the NS72, which is an out-of-order 64-bit RISC-V processor with the RVV vector extension.
RISC-V, with its open-standard Instruction Set Architecture (ISA), offers processor developers many options and configurable features, enabling the development of optimised domain-specific processors.
ImperasDV supports the RISC-V design verification tasks across the complete specification, plus custom instructions, with the Imperas RISC-V reference model, architectural validation tests, additional functional test suites, coverage analysis, and simulation-based test methodologies for asynchronous events and debug operations.
“The NSITEXE Akaria processors, developed with the use of Imperas RISC-V verification technology and the leading-edge SystemVerilog simulator and debug tools from Cadence, are targeted to address the high-performance requirements for AI and automotive requirements. The Akaria processors include the necessary features and quality to achieve the ISO 26262 ASIL D functional safety standard, in addition to being optimised and efficient processors for the next-generation embedded applications,” said Hideki Sugimoto, CTO of NSITEXE. “As the NSITEXE Akaria processors are adopted across a wide range of next-generation automotive, safety-critical, and embedded applications, the verification methodology with the support from Imperas and Cadence has been invaluable in achieving our quality goals and on-time development schedule.”
“By integrating our Xcelium Logic Simulator with Imperas's RISC-V verification technology, we've empowered NSITEXE to design the next-generation of its Akaria processors,” said Paul Cunningham, general manager of the System & Verification Group at Cadence.
“Processor verification is challenging, and yet critical to RISC-V adoption,” said Simon Davidmann, CEO at Imperas Software. “ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.”
