Engineering publications brought to you by Mark Allen

EDA & Design Software

Outlook 2013: Accelerating innovation and time to market

Chip design’s recycle cycle: Interview with Aart de Geus, chairman and co chief executive, Synopsys

How real number modelling is easing the analogue simulation challenge

Semiconductor R&D spending to hit record high in 2012

Cadence tests IP on TSMC’s 28nm processes

Improved interface speeds high frequency pcb design and analysis

Synopsys buys SpringSoft in $400million deal

SPICE simulator speeds analogue and rf designs

Cadence upgrades verification software

Balanced approach matches analogue design requirements

Cadence opens OrCAD Capture marketplace to all users

Metasimulator runs 100 times faster than Monte Carlo analyses